Integrated Circuits · Machine Learning Hardware · Hardware Security

About me

I am a postdoctoral researcher at Northeastern University, Department of Electrical and Computer Engineering. Prior to this, I obtained my Ph.D. in Electrical and Computer Engineering from the University of Illinois Urbana-Champaign (UIUC) in 2024, and my bachelor’s and master’s in Electronics and Electrical Communication Engineering from IIT Kharagpur in 2018.

Meeting AI’s growing computational demands requires accelerators that deliver high throughput with high energy efficiency. In-memory computing (IMC), a full-stack computing approach, addresses this challenge by performing computation directly in memory, reducing the energy cost of data movement. Realizing these gains requires algorithm-architecture-circuit co-design that accounts for how device and circuit properties affect inference accuracy. These same properties also influence model confidentiality and inference integrity, connecting accelerator design with hardware security.

My research builds on this connection through energy-efficient IMC design and investigations of confidentiality and integrity attacks on custom IMC chips and commercial AI accelerators, including GPUs. Understanding the hardware mechanisms behind these attacks guides protections against leakage and malicious computation, feeding security requirements back into architecture and circuit design. My long-term goal is to design low-power AI accelerators for emerging AI workloads on resource-constrained platforms, treating security and energy efficiency as joint design requirements. Some of my recent works are:

Energy-efficient eNVM in-memory computing accelerator design

1. a compositional benchmarking framework that compares over 100 IMC and digital chips using bit-normalized throughput, energy efficiency, and compute density (OJ-SSCS 2022, CICC 2022).
2. statistical models of resistive IMCs for MRAM, ReRAM, and FeFET, which set their compute-SNDR limits and energy-accuracy trade-offs (JxCDC 2024, ISCAS 2022).
3. an accuracy-boosted 22 nm MRAM IMC macro that raises compute SNDR through offset-compensating current sensing and statistical error compensation (JSSC 2024, ESSCIRC 2023).

Security vulnerabilities of ML accelerators

1. DNN backdoor attacks using Rowhammer-induced DRAM bit flips, and a defense that places model weights away from vulnerable memory pages (ICCAD 2026).
2. Side-channel attacks through the Apple M1’s shared CPU–GPU cache (CCS 2026), and unsupervised transfer learning for cryptographic key recovery across devices and measurement types (AsiaCCS 2026).
3. the energy-accuracy-security trade-offs in resistive IMCs, where analog noise lowers compute SNDR but does not protect stored weights from model extraction attacks (TCAD 2026, IEDM 2024, ICCAD 2024).
4. hardware-Trojan detection that repurposes existing on-chip differential temperature sensors in a 65 nm ASIC (TCAS-I 2026).

News

• Nov 2026SLAC, on CPU-to-GPU side-channel attacks on Apple Silicon, to appear at CCS 2026.
• Nov 2026ROBBIN, on Rowhammer-based backdoor injection during inference, to appear at ICCAD 2026.
• Nov 2026I will serve as a session chair at ICCAD 2026.
• Oct 2026CAPER, on circuit-aware parameter-efficient reasoning in LLMs for analog verification, will be presented as a poster at IBM/IEEE AICS 2026.
• Sep 2026Profiled in Humans of NanoSI at Northeastern University, with a short video.
• Sep 2026HOTSPOT, on detecting on-chip Trojans through temperature sensing, published in TCAS-I.

All news and talks