Updates and talks

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon

To appear at the ACM SIGSAC Conference on Computer and Communications Security (CCS) · The Hague, Netherlands.

ROBBIN: Rowhammer-Based Backdoor Injection during Inference

To appear at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) · San Jose, California.

Session Chair at ICCAD 2026

I will serve as a session chair at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) · San Jose, California.

CAPER: Circuit-Aware Parameter-Efficient Reasoning in LLMs for Analog Verification

To be presented at the IBM/IEEE AI Compute Symposium (AICS 2026) · IBM T.J. Watson Research Center, Yorktown Heights, New York.

Humans of NanoSI: Saion K. Roy

Profiled by the Institute for NanoSystems Innovation (NanoSI) at Northeastern University · Online.

Profile·Video

HOTSPOT: Hardware Observation via Temperature Sensing for Protection against On-Chip Trojans

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I).

Comprehending the Energy-Accuracy-Security Trade-offs in Embedded Non-Volatile In-Memory Computing Architectures

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

Attack from Shadows: Unsupervised Side-channel Transfer Learning across Devices and Modalities

Published and presented at the ACM Asia Conference on Computer and Communications Security (AsiaCCS) · Bangalore, India.

Energy-Accuracy-Security Trade-offs in Resistive In-Memory Computing Architectures

Presented at the SRC JUMP 2.0 COCOSYS Annual Review · Georgia Institute of Technology, Atlanta, Georgia · March.

Presented at New England Hardware Security Day · Massachusetts Institute of Technology, Cambridge, Massachusetts · April.

Presented at the Recent Advances in Artificial Intelligence for National Security (RAAINS) Workshop · MIT Lincoln Laboratory, Lexington, Massachusetts · November.

Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures

Presented at the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) Open Journal Webinar · Online.

Saion K. Roy: Graduate Spotlight

Featured in the SRC JUMP 2.0 COCOSYS Graduate Spotlight · Online.

The Energy-Accuracy-Security Trade-off in Resistive In-memory Architectures

Published at the IEEE International Electron Devices Meeting (IEDM).

On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks

Published and presented at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) · Newark, New Jersey.

Security Vulnerabilities of eNVM-based In-memory Architectures

Presented at SRC JUMP 2.0 COCOSYS · Online.

Compute SNDR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation

Published in the IEEE Journal of Solid-State Circuits (JSSC).

Energy-Accuracy Trade-offs for Resistive In-Memory Computing Architectures

Presented at SRC JUMP 2.0 COCOSYS · Online · May.

Presented at the Indian Institute of Technology Madras · Chennai, India · August.

Energy-Accuracy Trade-offs for Resistive In-Memory Computing Architectures

Published in the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC).

Compute SNDR-boosted 22 nm MRAM IMC using Statistical Error Compensation

Presented at SRC JUMP 2.0 COCOSYS · Online.

GPLeak: Software Power Side Channel Leakage in GPUs

Presented at the Coordinated Science Laboratory Student Conference · University of Illinois Urbana-Champaign, Urbana, Illinois · Oral Presentation Award.

Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation

Published and presented at the IEEE European Solid-State Circuits Conference (ESSCIRC) · Lisbon, Portugal.

Fundamental Limits on the Compute SNR of Resistive In-Memory Architectures

Presented at the Coordinated Science Laboratory Student Conference · University of Illinois Urbana-Champaign, Urbana, Illinois · Best Speaker Award.

Benchmarking In-memory Computing Architectures

Published in the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS).

Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures

Published and presented at the IEEE International Symposium on Circuits and Systems (ISCAS) · Austin, Texas · Student Participation Grant.

Comprehending In-memory Computing Trends via Proper Benchmarking

Published at the IEEE Custom Integrated Circuits Conference (CICC).